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-- Implemetacion de un registro de memoria de 5 bits
-- Amilcar J., Erazo P.
----------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

--Entidad registro de 12 bits

entity reg12bits is
	port (
		D_i   : in std_logic_vector (11 downto 0);
		CLK_i : in std_logic;
        E_i   : in std_logic;
		Q_o   : out std_logic_vector (11 downto 0) );
end reg12bits;

architecture behavioral of reg12bits is
begin 
	process ( CLK_i )
	begin
		if CLK_i = '1' and CLK_i'event then
            if (E_i = '1') then
    			Q_o <= D_i;
            end if;
		end if;
	end process;
end behavioral;

-- vim: tabstop=4 : shiftwidth=4 : expandtab
